To remedy this problem, we introduce two new workload-driven DVFS techniques that utilize hardware events, (i) the percentage of all stalls (FS-Total Stalls) and (ii) the percentage of memory-related stalls (FS-Memory Stalls), linearly mapping them into available clock frequencies every 10 ms. We find that the processor operates at the highest clock frequency even when ~90% of all active CPU cycles are stalled, resulting in poor energy-efficiency, especially in the case of memory-intensive benchmarks. In this paper, we describe the results of a study that explores the effectiveness of the existing DVFS governors by measuring performance, energy efficiency, and the product of performance and energy efficiency (P圎E), when running both the speed and throughput SPEC CPU2017 benchmark suites.
PARSEC BENCHMARK DRIVERS
Modern processors support dynamic voltage and frequency scaling (DVFS) that can be leveraged by BIOS or OS drivers to regulate energy consumed in run-time. We elucidate the advantages and disadvantages of each of the proposed techniques and offer guidelines on when to use them. Further, we find that the proposed techniques are especially effective for memory-intensive benchmarks, wherein EE improves from 121% to 183% and P圎E from 100% to 141%. The results of the experimental evaluation show that the proposed techniques significantly improve EE and P圎E metrics relative to the state-of-the-art approaches. The proposed techniques linearly map these metrics into available processor clock frequencies. To remedy this problem, we introduce, implement, and evaluate the effectiveness of four new DVFS-based power management techniques driven by the following metrics derived from the processor’s performance monitoring unit (PMU): (i) the percentage of all pipeline slot stalls (FS-PS), (ii) the percentage of all cycle stalls (FS-TS), (iii) the percentage of memory-related cycle stalls (FS-MS), and (iv) the number of last level cache misses per kilo instructions (FS-LLCM), respectively. For example, we find that the processor operates at the highest clock frequency even when 90% of all processor cycles are stalls, resulting in wasted energy. The results of this study indicate that the state-of-the-art DVFS power management techniques heavily favor performance, resulting in poor energy efficiency. In this dissertation, we first describe the results of our measurement-based study that evaluates the impact of the state-of-the-art power management techniques on performance (P), energy efficiency (EE), and their product (P圎E) in an Intel Core i7 processor, running SPEC CPU2017, Parsec-3.0, and SPECpower_ssj2008 benchmark suites. Typical power management techniques rely on either running the processor at a fixed clock frequency or utilizing dynamic voltage and frequency scaling (DVFS) techniques that adjust the processor’s clock frequency in runtime based on its current level of activity.
PARSEC BENCHMARK DRIVER
The processor is the primary driver of the overall system power consumption of a computer system. Energy-efficient computing is one of the most important challenges computer designers and operators are facing today, exacerbated by the ever-increasing demands for faster, smaller, lighter, and more affordable computing.
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